<?xml version="1.0" encoding="UTF-8"?>
<Project>
    <Project_Created_Time>2020-07-23 20:19:40</Project_Created_Time>
    <TD_Version>4.6.18154</TD_Version>
    <UCode>01010100</UCode>
    <Name>eg4</Name>
    <HardWare>
        <Family>EG4</Family>
        <Device>EG4S20BG256</Device>
    </HardWare>
    <Source_Files>
        <Header/>
        <Verilog>
            <File>../rtl/eg4_top.v</File>
            <File>../../lib/config.v</File>
            <File>../../lib/wbc_lsi.v</File>
            <File>../../lib/wbc_rst.v</File>
            <File>../../lib/wbc_uart.v</File>
            <File>../../lib/wbc_vic.v</File>
            <File>../../lib/wbc_vm1.v</File>
            <File>../../lib/wbc_vm2.v</File>
            <File>../../lib/wbc_vm3.v</File>
            <File>../../lib/wbc_am4.v</File>
            <File>../../lib/wbc_f11.v</File>
            <File>../../../lsi/hdl/wbc/rtl/lsi_wb.v</File>
            <File>../../../lsi/hdl/wbc/rtl/mcp_plm.v</File>
            <File>../../../lsi/hdl/wbc/rtl/mcp1611.v</File>
            <File>../../../lsi/hdl/wbc/rtl/mcp1621.v</File>
            <File>../../../vm1/hdl/wbc/rtl/vm1_plm.v</File>
            <File>../../../vm1/hdl/wbc/rtl/vm1_reg.v</File>
            <File>../../../vm1/hdl/wbc/rtl/vm1_tve.v</File>
            <File>../../../vm1/hdl/wbc/rtl/vm1_wb.v</File>
            <File>../../../vm2/hdl/wbc/rtl/vm2_plm.v</File>
            <File>../../../vm2/hdl/wbc/rtl/vm2_wb.v</File>
            <File>../../../vm3/hdl/wbc/rtl/vm3_plm.v</File>
            <File>../../../vm3/hdl/wbc/rtl/vm3_wb.v</File>
            <File>../../../am4/hdl/wbc/rtl/am4_alu.v</File>
            <File>../../../am4/hdl/wbc/rtl/am4_plm.v</File>
            <File>../../../am4/hdl/wbc/rtl/am4_seq.v</File>
            <File>../../../am4/hdl/wbc/rtl/am4_wb.v</File>
            <File>../../../f11/hdl/wbc/rtl/dc_302.v</File>
            <File>../../../f11/hdl/wbc/rtl/dc_303.v</File>
            <File>../../../f11/hdl/wbc/rtl/dc_304.v</File>
            <File>../../../f11/hdl/wbc/rtl/dc_pla.v</File>
            <File>../../../f11/hdl/wbc/rtl/dc_pla_0.v</File>
            <File>../../../f11/hdl/wbc/rtl/dc_pla_1.v</File>
            <File>../../../f11/hdl/wbc/rtl/dc_pla_2.v</File>
            <File>../../../f11/hdl/wbc/rtl/f11_wb.v</File>
            <File>../rtl/eg4_tlib.v</File>
            <File>../rtl/vm1_tlib.v</File>
            <File>../rtl/vm3_tlib.v</File>
            <File>../rtl/lsi_tlib.v</File>
            <File>../rtl/am4_tlib.v</File>
            <File>../rtl/f11_tlib.v</File>
        </Verilog>
        <ADC_FILE>eg4.adc</ADC_FILE>
        <SDC_FILE>eg4.sdc</SDC_FILE>
        <CWC_FILE/>
    </Source_Files>
    <TOP_MODULE>
        <LABEL/>
        <MODULE>eg4</MODULE>
        <CREATEINDEX>user</CREATEINDEX>
    </TOP_MODULE>
    <Property>
        <BitgenProperty::GeneralOption>
            <s>off</s>
        </BitgenProperty::GeneralOption>
        <GlobalProperty>
            <message>verbose</message>
        </GlobalProperty>
        <TimingProperty/>
        <RouteProperty>
            <opt_timing>high</opt_timing>
        </RouteProperty>
        <DesignProperty/>
        <RtlProperty/>
        <GateProperty>
            <opt_timing>high</opt_timing>
            <report>verbose</report>
        </GateProperty>
        <PlaceProperty>
            <opt_timing>high</opt_timing>
        </PlaceProperty>
        <SimProperty/>
    </Property>
    <Project_Settings>
        <Step_Last_Change>2024-08-18 13:43:24</Step_Last_Change>
        <Current_Step>60</Current_Step>
        <Step_Status>true</Step_Status>
    </Project_Settings>
</Project>
