<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
    <FileList>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_302.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_303.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_304.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_fpp.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_mmu.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_pla.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_pla_0.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_pla_1.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_pla_2.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/dc_rom.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/f11/hdl/wbc/rtl/f11_wb.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/xen/lib/config.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/xen/lib/wbc_f11.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/xen/lib/wbc_rst.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/xen/lib/wbc_uart.v" type="file.verilog" enable="1"/>
        <File path="/home/yu/work/cpu11/xen/lib/wbc_vic.v" type="file.verilog" enable="1"/>
        <File path="rtl/f11_defs.v" type="file.verilog" enable="1"/>
        <File path="rtl/gwn_mem.v" type="file.verilog" enable="1"/>
        <File path="rtl/sn9_top.v" type="file.verilog" enable="1"/>
        <File path="src/mem_f11/mem16x16k_f11.v" type="file.verilog" enable="1"/>
        <File path="syn/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
        <File path="syn/nano9k.cst" type="file.cst" enable="1"/>
        <File path="src/cpu11.sdc" type="file.sdc" enable="1"/>
        <File path="src/mem_f11/mem16x16k_f11.ipc" type="file.other" enable="1"/>
        <File path="src/mem_f11/mem16x16k_f11.mod" type="file.other" enable="1"/>
    </FileList>
</Project>
